5/19/2023 0 Comments Parity prediction bit slicer![]() The logic for the column- parity and IC-signal generation is outlined in Fig. When a data word is changed the IC-signal is raised to recalcu- late the parity vectors. Column- and diagonal-parity predictions are triggered by internal change (IC) signals that are strongly clock dependent. ![]() For row-parity prediction, the input for the prediction logic comes from the register input bus. ![]() A prediction logic needs to be implemented for on-line observation. Cross-parity check refers to the com- bined check of row- column- and diagonal-parity. Even or odd parity is calculated by simply XORing or XNORing the corresponding row, column or diago- nal (Fig. For detection of multiple errors, at least three parity vectors have to be calculated: row -parity r X, column -parity c Y and diagonal -parity d Z. The EDAC can be performed by software routines or additional hardware. It is capable of detecting multiple bit-errors in storage elements - especially register files or register groups - by logical interpretation of cross-parity vectors. A mechanism for error detection and correction (EDAC) that uses cross-parity is proposed in. This correction technique also has to cope with SEUs in the Code Checker. Different implementations based on error correcting codes or recalculation are possible. As the proposed method only indicates an error, an additional error correction mechanism has to be implemented. 27 presents the achieved soft error failure rate reduction when different area overhead values are applied to the algorithm. The heuristic algorithm for choosing the nodes to be duplicated selects nodes with high susceptibility as long as the favoured maximum area overhead is not reached. On the other hand, if any SEU occurs at a node in the partially duplicated part (in either the function logic or the cutset), the outputs differ and the errror is detected at the checker. Hence, when an upset in the non-duplicated portion occurs and a sensitized path to the outputs exist, the error will not be detected. As the susceptibility of the non-duplicated part is very low, the inputs to both cutset circuits are the same and come from the non-replicated part. part together with a Cutset Logic that is also presented as a duplicated circuit.
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